What do the guys say?
Engineers should rely on literature, simulations, and academic facts. On the other hand, when experienced engineers are around us, it is often easier for us to rely on the experienced guys.
In every course I teach in the field of High-Speed, I start with a few questions like:
What makes a signal a High-Speed signal?
What is the parameter that determines it's High Speed?
Can a mathematical relationship be found between this parameter and other parameters?
...The guys answer:
"Over 100MHz".
"Over a few hundred Mega Herz and above".
"It depends on the Rise Time".
What is the correct answer?
To answer the question, one needs to remember a few facts:
As digital board design engineers, we deal with square waves.
Square waves can be decomposed into a sum of sine waves of odd harmonics, each with a coefficient. (Fourier transform).
Empirical results show that the relationship between the Rise Time and the bandwidth (BW) can be calculated with a good approximation using a simple formula, see Figure 1 (The relationship between Rise Time and BW).
Examples from the "day-to-day" of the Board Designers
DDR3
In DDR3 components, the Rise Time is about 350psec. Based on this formula, the bandwidth of such a signal is 1GHz, meaning that the significant harmonics composed of the signal is found in a bandwidth of 1GHz. Well, it's well-known that DDR3 reaches very high speeds, hence the reason.
But what about seemingly slow signals?
ICS553 Clock Buffer
For example, let's take a "simple" Clock Buffer from IDT, the ICS553. In the datasheet, on page 5, you can see the characteristics of AC operation at a voltage of 3.3V. Note that the maximum Rise Time is 1nsec, but the Typical is 0.6nsec, and there is no information about the minimum. (According to the formula, the bandwidth, according to the Typical in 0.6nsec, will be about 583MHz). Figure 2 describes the topology of a Point-to-Point connection of the Clock without terminations because this is supposedly a "low frequency."
Figure 3 describes what happens when the line is oscillated at a "low" frequency of 1MHz. An overshoot reaches about 5V when the signal is 3.3V, and there is also ringing.
Conclusions
Nowadays, every digital design must be treated as a High-Speed signal.
Consequently:
Every signal should be designed with Controlled Impedance.
Terminations are necessary, especially for clock lines, even if they oscillate at "low frequencies."
Figure 1 - The relationship between Rise Time and BW
Figure 2 - The relationship between Rise Time and BW
Figure 3 - 1 MHz Clock Waveforms